(a) Fields of the Invention
The present invention relates to semiconductor devices. In particular, the present invention relates to semiconductor devices having transistors for electrostatic discharge (ESD) protection.
(b) Description of Related Art
In recent years, in semiconductor integrated circuit devices, elements therein have become finer and denser, and thus a high degree of integration thereof has been proceeding. Accompanied with this trend, the devices become sensitive to damages caused by electrostatic discharge (referred hereinafter to as surge). For example, there is a growing possibility that surge entering from a pad for external connection breaks elements included in an input circuit, an output circuit, an input/output circuit, and in addition an internal circuit and the like and thus performances of the elements are degraded. To avoid this possibility, in the semiconductor integrated circuit device, an electrostatic discharge (ESD) protection transistor for protecting the device against surge as disclosed in, for example, Japanese Unexamined Patent Publication No. H2-271673 is provided between the external connection pad and the input circuit, the output circuit, the input/output circuit, or the internal circuit.
FIGS. 17A and 17B are views of a conventional ESD protection transistor. FIG. 17A shows a plan structure thereof, and FIG. 17B shows a cross-sectional structure taken along the line XVIIb-XVIIb in FIG. 17A.
Referring to FIGS. 17A and 17B, an ESD protection transistor 50 includes: a well region 1 formed in an upper portion of a semiconductor substrate (not shown); a gate electrode 3 formed above the well region 1 with a gate oxide film 2 interposed therebetween; a drain region 4 as a high-concentration impurity diffusion layer formed in a portion of the well region 1 located below one side of the gate electrode 3; and a source region 5 as a high-concentration impurity diffusion layer formed in a portion of the well region 1 located below the other side of the gate electrode 3.
The drain region 4 is connected through a plurality of drain contacts 6A to 6E to a metal interconnect 8. The plurality of drain contacts 6A to 6E are formed in an interlayer insulating film 10, and the metal interconnect 8 makes connection to, for example, an input/output terminal (a pad for external connection) 11. The source region 5 is connected through a plurality of source contacts 7A to 7E to a metal interconnect 9. The plurality of source contacts 7A to 7E are formed in the interlayer insulating film 10, and the metal interconnect 9 makes connection to a reference voltage terminal (for example, a ground terminal or a power supply terminal) 12.
The plurality of drain contacts 6A to 6E and the plurality of source contacts 7A to 7E are spaced apart in the gate width direction, respectively. The drain contacts 6A to 6E and the source contacts 7A to 7E have the same intervals, and are formed to face each other with the gate electrode 3 interposed therebetween. Thus, as shown in FIG. 17B, the cross section of the gate electrode 3 taken along the gate length direction contains both of the drain contact 6C and the source contact 7C.
In the ESD protection transistor 50, when surge enters from the input/output terminal 11 connected to the drain region 4, the ESD protection transistor 50 is activated. In response to this, the surge entering from the outside is dissipated to the reference voltage terminal 12 connected to the source region 5, which enables protection of the internal circuit of the device.
In order for the conventional ESD protection transistor 50 to ensure a high ESD tolerance, for example, the current capability (the current-handling capability) of the order of amperes is required with respect to the surge applied for 100 ns or less.
To allow a current of the order of amperes to flow through the ESD protection transistor, a plurality of drain contacts and a plurality of source contacts should be arranged in the transistor width (gate width) direction for the purpose of preventing possible breaks in the contacts due to electromigration and stress migration.
To deal with this challenge, one of conventionally-employed methods for arranging a plurality of contacts both in the drain region and the source region of the ESD protection transistor is a method for arranging the contacts to keep a design rule minimum (D.R.M.) for contacts.
When the intervals between the contacts are narrowed, the parasitic resistance between the drain contacts adjoining in the transistor width (gate width) direction decreases. As a result of this, for example, currents from the drain contacts 6B and 6D easily enter a current flowing between the drain contact 6C and the source contact 7C. Thus, such local concentration of surge current on the source contact 7C causes thermal breakdown of the transistor, which disadvantageously results in degradation of the ESD tolerance of the device.